CLRC66303HNY board bring-up record
================================
Blank engineering worksheet — not a report of completed hardware tests.
Expected values below are guide references; confirm the current NXP datasheet.

BOARD AND TEST SETUP
Date / engineer:
Board revision / assembled part marking / traceability:
Schematic revision / PCB stack-up:
MCU / firmware commit or build / SPI rate:
Supply source / current limit / ambient temperature:
Antenna revision / matching components / enclosure:
Card or credential technology / part / orientation:
Instrument model / probe / capture file locations:

1. POWER
Expected: VDD/PVDD/TVDD meet the applicable limits; PVDD does not exceed VDD.
AVDD and DVDD are buffered internal nodes, not externally driven rails.
Observed rail values and startup/shutdown waveforms:
TVDD minimum during field activation / current step:
Pass, fail or unresolved / next action:

2. RESET AND INTERFACE
Expected: PDOWN sequence follows the datasheet; SPI straps are stable during
interface detection (IFSEL0 low, IFSEL1 high).
Observed pin levels / timing / relevant capture:
Pass, fail or unresolved / next action:

3. CLOCK
Expected: the specified 27.12 MHz oscillator starts reliably.
Observation method / probe loading / evidence:
Pass, fail or unresolved / next action:

4. SPI REGISTER ACCESS
Expected: Mode 0, MSB first. One low NSS interval covers MOSI FF 00.
The second MISO byte is 1A for CLRC66303; NSS returns high between commands.
Observed byte sequence / NSS boundaries / capture:
Number of attempts / successful reads / unexpected values:
Result with RF disabled / result while RF switches:
Pass, fail or unresolved / next action:

5. COMMANDS, IRQ AND FIFO
Command / protocol / configuration source:
Expected completion event / timeout:
Observed IRQ flags / error flags / FIFO bytes:
Pass, fail or unresolved / next action:

6. RF AND ANTENNA
Transmitter configuration / analog settings / matching revision:
Field-observation method / supply under load:
Measured RF-network response / receive-path evidence:
Pass, fail or unresolved / next action:

7. COMPLETE CARD EXCHANGE
Requested transaction / expected response:
Allowed distance / lateral offset / angle:
Latency limit / retry policy / required success criterion:
Attempts / successful complete exchanges / latency observations:
Supply and temperature conditions / enclosure and nearby metal:
Pass, fail or unresolved / next action:

DECISION
First unresolved stage:
Single variable to change in the next experiment:
Evidence needed before proceeding:
Responsible reviewer / next review date:

Reference: https://www.nxp.com/docs/en/data-sheet/CLRC663.pdf
Guide: https://www.nyfea.com/news/clrc66303hny-alternative-nf663.html

The supplied C example checks register transport; it is not a complete card
reader application. This worksheet does not establish NF663 compatibility.