SN74LVC1G00 Single 2-Input Positive-NAND Gate
NYFEA SN74LVC1G00 is a single 2-input positive-NAND gate specified for 1.65 V to 5.5 V operation. It accepts input voltages up to 5.5 V, supports Ioff partial-power-down operation and is offered in green SOT23-5 and SC70-5 packages.
Product scope: In positive logic, the device implements Y = ¬(A · B). Y is LOW only when both A and B are HIGH. It is a push-pull NAND gate, not a Schmitt-trigger input, open-drain output, tri-state buffer or analog switch.
Use the current controlled PDF for threshold limits, output loading, switching conditions, package tolerances, tape orientation and production-release decisions.
Product Overview and Selection Scope
SN74LVC1G00 integrates one 2-input positive-NAND gate. The output is LOW only when A and B are both HIGH. The specified operating supply is 1.65 V to 5.5 V, while the input operating range extends from 0 V to 5.5 V. This separation permits a higher input voltage than VCC within the recommended range, but system-level sequencing and signal-current paths still require validation.
Signal role
Inputs A and B drive one push-pull output Y. There is no output-enable or high-impedance control state.
Voltage domain
VCC is 1.65 V to 5.5 V for operation. VIH and VIL limits change with VCC; use the complete threshold table.
Power-down behavior
Ioff is specified with VCC = 0 V and VI or VO = 5.5 V to limit backflow through the powered-down device path.
Package choice
SOT23-5 and SC70-5 are both listed, each with its own ordering code, top marking, land pattern and thermal impedance.
Selection boundary: The PDF does not specify Schmitt-trigger hysteresis, open-drain operation, tri-state control, wired logic, analog switching or end-product qualification. Select another function when any of those behaviors is required.
Logic Function, Truth Table and Pin Assignment
In positive logic, Y = ¬(A · B) = ¬A + ¬B. Y is HIGH for three of the four valid input combinations and LOW only for A = HIGH and B = HIGH.
| Pin | Name | Type | Function | Engineering note |
|---|---|---|---|---|
| 1 | A | Input | First positive-logic input | Hold at VCC or GND when unused. |
| 2 | B | Input | Second positive-logic input | Hold at VCC or GND when unused. |
| 3 | GND | Power | Ground | Use a short return to the local bypass capacitor. |
| 4 | Y | Output | Push-pull NAND output | Do not connect to another active output. |
| 5 | VCC | Power | Supply | Place local decoupling near pins 5 and 3. |
Ordering Codes and Package Selection
| Ordering number | Temperature range | Package | Top marking | MSL | Packing |
|---|---|---|---|---|---|
| SN74LVC1G00DCKR | -40 °C to +125 °C | SC70-5 / SOT353 equivalent | CA5 | MSL 3 | Tape and reel, 3,000 units |
| SN74LVC1G00DBVR | -40 °C to +125 °C | SOT23-5 | C00K | MSL 3 | Tape and reel, 3,000 units |
Additional lot, date, vendor, logo or environmental markings may appear. Confirm the full order code, package dimensions, marking and reel orientation during receiving inspection.
Recommended Operating Conditions and Absolute Limits
Recommended operating conditions define the functional design range. Absolute maximum ratings are stress limits only and do not establish normal operation or long-term reliability.
| Parameter | Condition | Minimum | Maximum | Unit |
|---|---|---|---|---|
| Supply voltage, VCC | Operating | 1.65 | 5.5 | V |
| Supply voltage, VCC | Data retention only | 1.5 | 5.5 | V |
| Input voltage, VI | Operating | 0 | 5.5 | V |
| Output voltage, VO | Operating | 0 | VCC | V |
| Input rise/fall, tr or tf | VCC = 1.8 V ±0.15 V or 2.5 V ±0.2 V | - | 20 | ns/V |
| Input rise/fall, tr or tf | VCC = 3.3 V ±0.3 V | - | 10 | ns/V |
| Input rise/fall, tr or tf | VCC = 5 V ±0.5 V | - | 5 | ns/V |
| Ambient temperature, TA | Operating | -40 | 125 | °C |
Absolute maximum and handling limits
| Parameter | Condition | Minimum | Maximum | Unit |
|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 6.5 | V |
| Input voltage | VI | -0.5 | 6.5 | V |
| Output voltage | High-impedance or power-off state | -0.5 | 6.5 | V |
| Output voltage | HIGH or LOW state | -0.5 | VCC + 0.5 | V |
| Input clamp current | VI < 0 V | -50 | mA | |
| Output clamp current | VO < 0 V | -50 | mA | |
| Continuous output current | IO | ±50 | mA | |
| Continuous VCC or GND current | - | ±100 | mA | |
| Junction temperature | TJ | -65 | 150 | °C |
| Storage temperature | Tstg | -65 | 150 | °C |
DC Characteristics and Logic Levels
Unless otherwise noted, full-range limits apply from -40 °C to +125 °C. Typical values are characterized at +25 °C and are not guaranteed production limits.
| VCC range | VIH minimum | VIL maximum | Engineering interpretation |
|---|---|---|---|
| 1.65 V to 1.95 V | 0.65 × VCC | 0.30 × VCC | Thresholds scale with supply. |
| 2.3 V to 2.7 V | 1.7 V | 0.7 V | Use the fixed guaranteed limits. |
| 3.0 V to 3.6 V | 2.2 V | 0.8 V | Use the fixed guaranteed limits. |
| 4.5 V to 5.5 V | 0.70 × VCC | 0.30 × VCC | Thresholds scale with supply. |
Output levels, leakage and supply current
| Parameter | Test condition | VCC | Temperature | Limit or typical value | Unit |
|---|---|---|---|---|---|
| VOH | IOH = -100 µA | 1.65 V to 5.5 V | Full | Minimum VCC - 0.1 V | V |
| VOH | IOH = -4 / -8 / -16 / -24 / -32 mA | 1.65 / 2.3 / 3.0 / 3.0 / 4.5 V | Full | Minimum 1.2 / 1.9 / 2.4 / 2.3 / 3.8 V | V |
| VOL | IOL = 100 µA | 1.65 V to 5.5 V | Full | Maximum 0.1 V | V |
| VOL | IOL = 4 / 8 / 16 / 24 / 32 mA | 1.65 / 2.3 / 3.0 / 3.0 / 4.5 V | Full | Maximum 0.45 / 0.30 / 0.40 / 0.55 / 0.55 V | V |
| II | A or B at 5.5 V or GND | 0 V to 5.5 V | +25 °C / Full | Typical ±0.1 µA / maximum ±5 µA | µA |
| Ioff | VI or VO = 5.5 V | 0 V | +25 °C / Full | Typical ±0.1 µA / maximum ±10 µA | µA |
| ICC | VI = 5.5 V or GND, IO = 0 | 1.65 V to 5.5 V | +25 °C / Full | Typical 0.1 µA / maximum 10 µA | µA |
| ΔICC | One input at VCC - 0.6 V; other at VCC or GND | 3 V to 5.5 V | Full | Maximum 500 µA | µA |
AC Switching and Test Conditions
The propagation-delay values below are full-temperature maximum limits under the stated supply, load and resistance conditions. Input capacitance and power-dissipation capacitance are typical values at +25 °C.
| Parameter | VCC | Load condition | Temperature | Maximum / typical | Unit |
|---|---|---|---|---|---|
| Propagation delay, tpd | 1.8 V ±0.15 V | CL = 30 pF, RL = 500 Ω | Full | 21 maximum | ns |
| Propagation delay, tpd | 2.5 V ±0.2 V | CL = 30 pF, RL = 500 Ω | Full | 7.8 maximum | ns |
| Propagation delay, tpd | 3.3 V ±0.3 V | CL = 50 pF, RL = 500 Ω | Full | 5.7 maximum | ns |
| Propagation delay, tpd | 5.0 V ±0.5 V | CL = 50 pF, RL = 500 Ω | Full | 4.2 maximum | ns |
| Input capacitance, Ci | 3.3 V | VI = VCC or GND | +25 °C | 4 typical | pF |
| Power-dissipation capacitance, Cpd | 1.8 / 2.5 / 3.3 / 5.0 V | f = 10 MHz | +25 °C | 21 / 22 / 22 / 25 typical | pF |
Applicability note: The PDF includes generic enable/disable waveform templates, but SN74LVC1G00 has no output-enable pin. Do not infer tri-state operation from those generic diagrams.
Power Integrity, Input Handling and PCB Layout
The following layout is application guidance rather than a guaranteed reference circuit. Use the electrical tables for limits and validate the complete board power-distribution network and receiving logic interface.
- Do not leave inputs floating: the PDF requires unused inputs to be held at VCC or GND.
- Apply the correct edge-rate limit: the maximum tr/tf entry changes from 20 ns/V at low supply to 5 ns/V at 5 V.
- Check receiving VIH: a 5.5 V-tolerant input does not guarantee that a low-VCC output can drive every higher-voltage receiver.
- Budget transition current: ΔICC is listed as 500 µA maximum under the stated VCC - 0.6 V input condition.
- Prevent output contention: Y is push-pull and has no output-enable control.
- Validate partial power-down: Ioff limits the device path; other PCB components can still create back-power paths.
SOT23-5 and SC70-5 Packages, Land Patterns and Packing
Both green package options share the same logical pin assignment but use different body dimensions, lead pitch, top marking and thermal impedance. Do not substitute one footprint for the other.
| Dimension | SOT23-5 | SC70-5 | Unit |
|---|---|---|---|
| Overall height A | 1.050 to 1.250 | 0.900 to 1.100 | mm |
| Body length D | 2.820 to 3.020 | 2.000 to 2.200 | mm |
| Body width E | 1.500 to 1.700 | 1.150 to 1.350 | mm |
| Overall lead span E1 | 2.650 to 2.950 | 2.150 to 2.450 | mm |
| Lead pitch e | 0.950 BSC | 0.650 BSC | mm |
| Outer lead pitch e1 | 1.800 to 2.000 | 1.300 BSC | mm |
| Lead width b | 0.300 to 0.500 | 0.150 to 0.350 | mm |
| Lead length L | 0.300 to 0.600 | 0.260 to 0.460 | mm |
Application Guidance and Design Limitations
The Rev A.1 specification lists active noise elimination, barcode scanners, blood-pressure monitors, CPAP machines, fingerprint identification and network-attached storage. These are possible use contexts, not end-product approvals.
Active Noise EliminationCombine two digital qualification signals. The gate does not process the analog audio path.
Barcode ScannerCondition local interlock or ready states after checking edge rate, thresholds and load.
Blood Pressure MonitorUse only in non-safety logic paths after complete medical-system risk and qualification review.
CPAP MachineCombine supervisory signals; do not treat this standard gate as a life-support safety element.
Fingerprint IdentificationCombine detect or enable conditions while respecting power-up and partial-power-down sequencing.
Network-Attached Storage (NAS)Use for compact board-level status or control logic, not high-speed serial data switching.SN74LVC1G00 Engineering FAQs
What logic function does SN74LVC1G00 implement?
It is one 2-input positive-NAND gate. Y = ¬(A · B), so Y is LOW only when both inputs are HIGH.
What supply range is recommended?
VCC is specified from 1.65 V to 5.5 V for operation. The separate 1.5 V to 5.5 V entry is identified as data retention only.
Can the inputs accept 5.5 V when VCC is lower?
The recommended input range is 0 V to 5.5 V and input leakage is characterized across VCC = 0 V to 5.5 V. Still verify output-level compatibility and all board-level sequencing paths.
Is SN74LVC1G00 a Schmitt-trigger NAND gate?
No. The specification does not provide hysteresis thresholds. Use a Schmitt-trigger-qualified device when slow or noisy input transitions require hysteresis.
Does the output support tri-state or open-drain operation?
No. Y is a push-pull output with no enable pin. Do not connect it to another actively driven output or use it for wired logic.
What are the maximum propagation delays?
Under the listed load conditions and full temperature range, tpd is 21 ns at 1.8 V, 7.8 ns at 2.5 V, 5.7 ns at 3.3 V and 4.2 ns at 5 V.
What does Ioff provide?
Ioff is specified with VCC = 0 V and VI or VO = 5.5 V, with ±10 µA maximum over the full temperature range. It limits the device path but does not eliminate other board-level back-power routes.
Which package should be selected?
SN74LVC1G00DBVR is SOT23-5 with C00K marking. SN74LVC1G00DCKR is SC70-5 with CA5 marking. Both are MSL 3 and packed 3,000 units per reel.
Can unused inputs be left open?
No. The PDF explicitly requires all unused inputs to be held at VCC or GND.
Do the listed applications establish product certification?
No. The application list identifies possible use contexts only. Qualification, safety, EMC, reliability and production validation remain system responsibilities.
This page summarizes the SN74LVC1G00 Rev A.1 product specification for component evaluation and engineering reference. It does not replace the complete controlled specification. Confirm the current revision, ordering code, marking, pin assignment, logic limits, absolute maximum ratings, DC and AC conditions, package tolerances, PCB layout, assembly process and qualification requirements before production release.
